Optimizing Power Efficiency in Embedded Systems

Introducing DOLPHIN DESIGN I-Stratus Low-power Cache Controller

Table of Contents

Cache concepts
Solving Cache Configuration Issues with I-Stratus LP
Conclusion

Introduction

The growing market demands for reduced power consumption in embedded systems and the increasing complexity of systems-on-chip call for innovative solutions. In microcontroller systems that use memories such as Flash, OTP, EPROM, or EEPROM, these memories can consume a significant portion of the system’s overall power. Incorporating a cache can offer two main benefits. Firstly, it can enhance speed by reducing memory latency and increasing throughput, which is the traditional approach. More importantly, if the cache is well-configured and designed with the right features, it can greatly reduce power consumption by optimizing memory accesses. For instance, using a Dolphin I-Stratus LP cache controller can reduce the power consumption of an embedded Flash in a 180 nm process by up to four times and halve its average access time.

Cache Concepts

In semiconductor manufacturing, process variation is an inevitable reality. Different process nodes, fabrication technologies, and foundries (GF, TSMC, SMIC and other) face variations in the manufacturing process, leading to performance discrepancies among individual devices. Silicon vendors provide models that describe the extreme operating conditions of each chip, allowing chipset designers to understand their performance boundaries. Those extreme operating condition are called Corner cases.

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