SMASH Mixed-Signal Simulator
Description
SMASH is a seamless IC-PCB mixed-signal simulator enabling the development and verification of analog and mixed-signal Silicon IPs and Integrated Circuits (IC) as well as the optimization of application schematics thanks to its unique multi-domain capabilities.
With the mixed-signal simulator SMASH, designers benefit from innovative features which enable efficient and fast detection of design defects with a fine control for tuning the speed accuracy trade-offs.
These features address the request from designers to rely on a simulator which can truly help them improve their design productivity for as faster and safer time-to-fab. Indeed, the analysis of the time spent by engineers to complete their designs shows that most of their valuable time can be saved with a simulator offering appropriate design bug detection features as well as debugging features.
SMASH is the mixed-signal simulator of choice for designers eager to improve their productivity!
Key Strengths
State-of-the-art single kernel for easy mixing of multi-language, mixed-signal and multi-domain descriptions
Support of the most common modeling languages: SPICE, (System)Verilog, VHDL, Verilog-A(MS), VHDL-AMS...
Support of different SPICE flavors including HSPICE compatibility
Automatic insertion of configurable interface devices as needed between logic and analog parts
Dynamic link with the schematic editor SLED
Back-annotation of operating-point states to the schematic
Cross-probing to quickly localize a signal curve
Simultaneous display of analog and logic simulation results in an interactive waveform viewer both interactively during the analysis runtime and in post-processing
Interoperability
Easy setup of trade-off between speed and accuracy plus added-value features for design bug detection and eradication
IEEE model encryption for source code protection in order to exchange data safely
Simulation results calibrated against Silicon measurements
Required flexibility to model the IC with its application schematics to optimize system performance as early as possible in the design cycle and before any fabrication
Compatibility with frameworks and complementary solutions (HSPICE, ModelSim, PSpice) to add new modeling and simulation capabilities to an existing design flow
SMASH integrated as Laysim in Laytools suite from TexEDA
Schematic-driven Layout between SLED and DW2000 from Design Workshop Technologies
Easy communication between S-Edit from Tanner EDA and SMASH
Evolution
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Version
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Description
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Presentation Sheet
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SMASH 7.6
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SMASH 7.6.0 mixed-signal simulator significantly speeds up OP/DC and transient analyses of analog and mixed designs in advanced nodes by a gain between x2 and x6. These major speed-up gains have been possible thanks to new methods and algorithms without losing simulation accuracy, as merge of identical SPICE instances, improve evaluation of MOS transistors, RC reduction methods and new Solver.
All these features allow SMASH to be as fast or even to overtake the major fastest golden spice simulators, while ensuring accuracy of a single solver SPICE simulator.
SMASH is now supporting SystemVerilog language for RTL synthesizable simulations, thanks to the integration of Verilator. Verilator is open source Verilog/SystemVerilog simulator. Verilator converts Verilog HDL modules to C++ models which are simulated by SMASH.
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SMASH 7.5
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SMASH 7.5.0 mixed-signal simulator speeds up transient analysis of leading-edge analog and mixed designs by up to 1.5X compared to previous release.
Moreover, with SMASH 7.5.0, convergence of OP and DC analyses has been strongly improved and speed up by 10X or more, especially for mixed-signal circuits.
Now SMASH 7.5.0 supports TSMC Model Interface (TMI) aging flow to simulate Hot Carrier injection (HCI) and Bias Temperature Instability (BTI) effects in design for reliability validations.
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SMASH 7.4
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With SMASH 7.4, for circuits with thousands of MOS devices in advanced process nodes and/or post-extractionRC, designer productivity has been enhanced by improving and accelerating transient analysis by a factor x2 and more without losing simulations accuracy. Moreover, for checking the stability of closed loop systems, SMASH 7.4 provides a new method “Zeq” to enable draw of any voltage node.
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SMASH 7.2 - New custom static electrical rules checking
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SMASH 7.2 provides new API functionalities to scan analog circuit across DEVICE connections and to verify your own custom Static Electrical Rules Checking.
An example part of the installation kit enables to detect automatically and quickly all MOS transistors with gates directly connected to supply sources, without launching any simulation.
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SMASH 7.1 - Optimize monte carlo analysis
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Accelerating Monte Carlo Analysis is crucial because designs in advanced process-node have much larger variation and need to run thousands or even millions of statistical simulations.
Thus, with SMASH 7.1, for circuits with thousands of MOS devices, Monte Carlo analysis has been sped-up by accelerating loading phase of each run by a factor of up to x3.Moreover, with SMASH 7.5.0, convergence of OP and DC analyses has been strongly improved and speed up by 10X or more, especially for mixed-signal circuits.
Now SMASH 7.5.0 supports TSMC Model Interface (TMI) aging flow to simulate Hot Carrier injection (HCI) and Bias Temperature Instability (BTI) effects in design for reliability validations.
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SMASH 7.0 - 64-bit native application
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Starting from now, all our EDA solutions will only be available in 64-bit versions for x86_64 platforms with Microsoft Windows Vista/7/8/10 or with RedHat Enterprise Linux 6 (RHEL6) and compatible Linux distributions.
Native 64-bit applications allow to overcome the limitations of 32-bit versions, such as loading large designs and simplifying installations on a 64-bit Linux OS.
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