Dolphin Semiconductor’s foundation IP platform brings embedded memories and standard-cell libraries, off-the-shelf from 180nm down to 40nm and optimized for leading foundry processes. The platform targets energy- and area-constrained SoCs by optimizing leakage, dynamic power and silicon area in the two building blocks every digital design depends on: logic libraries and embedded memories.
Foundation IP offers a combination of standard-cell logic libraries and embedded memory compilers that a chip maker can license instead of building its own physical-design foundation. Available off-the-shelf from 180nm down to 40nm and optimized for leading foundry processes, every block is delivered ready for place-and-route and physical verification on a customer SoC.
The platform is built around one requirement: a secured, cost-effective foundation for complex SoCs. Area, leakage and dynamic power are optimized at the cell and memory level instead of being fought late in the design flow.
Off-the-shelf node range
Smaller area
vs. 7-track library
Lower leakage
SESAME BiV
Power saving
SpRAM Rhea
Area saving
SpRAM Rhea
Figures are Dolphin design targets and silicon measurements published in the IP Catalog 2026.
Two families, logic libraries and embedded memories. Select a block to see what it brings.
Standard Cells Logic libraries
General-purpose logic library for digital synthesis and place-and-route.
Wearable devices
Up to 15% smaller area after P&R vs a standard 7-track library
Area-constrained low-power SoCs
SESAME uHD Logic libraries
Ultra-high-density logic library.
Wearable devices
Up to 30% higher density at cell level
Maximum-density digital cores
SESAME BiV Logic libraries
Bias-voltage logic library for always-on domains, without the need for a dedicated regulator.
Battery-powered IoT
100x lower leakage, 7x smaller area
Always-on IoT and wearable domains
SpRAM Rhea Embedded memories
Single and Dual Port SRAM compiler with multiple power modes.
Battery-powered IoT Complex multi-domain SoCs
Up to 30% area saving, 50% power saving
On-chip SRAM for low-power SoCs
Via-Programmable ROM Embedded memories
Patented bitcell ROM compiler, mask-programmable at the via layer.
Cost-sensitive consumer SoCs
Up to 20% area saving, 50% power saving
Firmware and code storage
Register Files Embedded memories
Compiled register-file memory for control and pipeline storage.
Complex multi-domain SoCs
Multiple power modes, fast wake-up
Control logic and pipeline storage
Key capabilities that optimize area, leakage and dynamic power at the cell and memory level, before the SoC reaches place-and-route.
Dense cell architectures and compact bitcells reduce die area, directly lowering per-unit manufacturing cost at volume.
Related blocks: Standard Cells, SESAME uHD, SpRAM Rhea, Via-Programmable ROM
Bias-voltage logic keeps always-on domains running at 100x lower leakage, without the need for a dedicated regulator.
Related blocks: SESAME BiV
Memory compilers offer several power modes with fast wake-up, so that each domain powers down independently.
Related blocks: SpRAM Rhea, Register Files
Linux-based compilers give wider instance-generation flexibility for memories sized to the design.
Related blocks: SpRAM Rhea, Via-Programmable ROM, Register Files
Each application is tied to the blocks and the specification that make it work.
SESAME BiV SpRAM Rhea
Always-on logic at 100x lower leakage removes the need for a dedicated regulator, and low-power SRAM extends battery life.
SESAME uHD Standard Cells
Ultra-high-density cells shrink digital core area in tightly space-constrained form factors.
Via-Programmable ROM
Mask-programmable at the via layer keeps mask cost down while storing firmware and code.
Register Files SpRAM Rhea
Multiple power modes on both memory families let each domain wake up and power down independently.
These blocks are off-the-shelf from 180nm down to 40nm and optimized for leading foundry processes. The exact node list for a given library or compiler is in its datasheet, available on request.
Dolphin licenses per project, with the option of per-unit royalties depending on the block and the volume. A licence covers the deliverable set needed for integration: views, models, documentation and integration support. Terms are set with the field engineering team during the technical evaluation.
SESAME uHD is an ultra-high-density library optimizing cell-level density. SESAME BiV is a bias-voltage library targeting always-on domains, cutting leakage 100x and area 7x without a dedicated regulator.
SpRAM Rhea (Single and Dual Port SRAM), Via-Programmable ROM with a patented bitcell, and Register Files, all with multiple power modes for SoC power optimization and fast wake-up.
Yes. Dolphin’s Application Lab supports pre-licence technical evaluation, including characterisation data review and integration feasibility on the target node. Requests go through the support channel below.
Yes. Linux-based compilers give wider instance-generation flexibility, and Dolphin’s design teams can adapt libraries and memories to a target node when the off-the-shelf configuration does not fit.
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